James Reinders

Systems Architect, Coventry Computer

James Reinders is systems architect at Coventry Computer, a startup in stealth mode, where he is responsible for software and hardware strategy, product engineering, system performance, benchmarking, and validation. He likes fast computers and the software tools to make them speedy.

James is an industry expert in parallel computing and high-performance computing, with over 30 years of experience. He has deep expertise in computer architecture and design, software development tools, Intel Xeon and Xeon Phi products (including Knights Ferry, Knights Corner, Knights Landing, and Knights Mill), compilers, and software design. He is an accomplished author, teacher, and business negotiator. He is a strong communicator with extensive experience as a technical speaker, public speaker to audiences of all types, expert spokesperson, and industry consultant.

James served as system architect for systolic arrays systems WARP and iWarp, the world's first TeraFLOP/s supercomputer (ASCI Red), and the world's first TeraFLOP/s microprocessor (Intel Xeon Phi Coprocessor, code-named Knights Corner). He has worked on compilers and architectures for multiple Intel processors and parallel systems. James is the inventor behind six patents in this area.

Until retiring from Intel in June 2016, James was Intel's chief software evangelist and leading spokesperson on tools for parallelism, frequently speaking at conferences, for user groups, and in customer engagement, as well as with press and analysts around the globe. Managing a worldwide team, he propelled Intel from obscurity to a leader in software development tools, with a powerful sales force and ground-breaking work in technical evangelism. He led Intel in both strong revenue growth and user-base growth.

James is the author of eight books in the HPC field, numerous papers, book chapters, and blogs. His books include VTune, Intel Threading Building Blocks, Structured Parallel Programming, Intel Xeon Phi Coprocessor Programming, Multithreading for Visual Effects, High Performance Parallelism Pearls Volume One and Volume Two, and Intel Xeon Phi Processor Programming, Knights Landing.

James lives in Oregon and loves the outdoors and history, especially through numismatics. He proudly graduated many years ago from the University of Michigan with a BSE in Electrical and Computing Engineering and an MSE in Computer Engineering. Go Blue!

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News for: James Reinders

Speaker at FiRe 2017

News Headlines  (10 of 12)
Seven AI habits IT can learn from HPC
Posted on 16 Aug 2019 at 1:58am

Top Ten Ways AI Affects HPC in 2019
Posted on 26 Mar 2019 at 9:10am

AI Is Reshaping Programming: Four Tips on How to Stay on Top
Posted on 29 Jan 2019 at 10:37am

Optimizing HPC Code with Roofline Analysis
Posted on 23 Oct 2018 at 5:13am

New Optimizations Improve Deep Learning Frameworks For CPUs
Posted on 13 Oct 2017 at 10:20am

Reinders: “AVX-512 May Be a Hidden Gem” in Intel Xeon Scalable Processors
Posted on 29 Jun 2017 at 7:35am

Intel’s VP of Datacenter Group on “AI—and More—on IA”
Posted on 15 Aug 2016 at 5:14am

Cheating on Moore to Get More
Posted on 11 Oct 2017 at 5:00pm

James Reinders Presents: Vectorization (SIMD) and Scaling (TBB and OpenMP)
Posted on 13 Oct 2015 at 5:00pm

James Reinders Leaving Intel and What It Means
Posted on 7 Jun 2016 at 5:00pm

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